Development Trends of Hybrid Bonding Technology and Applications in Semiconductors (pre-order)
As semiconductor chip components continue to shrink and circuit density increases, the size and spacing of signal interconnect electrodes are facing a constant demand for downsizing. This miniaturization trend poses even higher requirements for interconnect bonding technology in chip stacking. Currently, hybrid bonding stands out as the key technology that best meets these demands. This report examines the current development status of hybrid bonding technology, investigates its integration into various application chip packaging by industry players, and explores the future trends in technological advancements and applications.
Table of Contents
1. DEVELOPMENT OF HYBRID BONDING TECHNOLOGY
1.1 The Demand for High-Density OSAT Drives the Development of Microbumps
1.2 An Introduction to Hybrid Bonding Technology
2.CASE STUDIES OF HYBRID BONDING APPLICATIONS
2.1 Sony
2.2 AMD
2.3 Intel
3. MIC PERSPECTIVE
Appendix
List of Companies
1. DEVELOPMENT OF HYBRID BONDING TECHNOLOGY
1.1 The Demand for High-Density OSAT Drives the Development of Microbumps
1.2 An Introduction to Hybrid Bonding Technology
2.CASE STUDIES OF HYBRID BONDING APPLICATIONS
2.1 Sony
2.2 AMD
2.3 Intel
3. MIC PERSPECTIVE
Appendix
List of Companies
LIST OF FIGURES
Figure 1 Development of Block Size and I/O Count
Figure 2 Introduction to Hybrid Bonding Process
Figure 3 Sony's CIS (Complementary Metal-Oxide-Semiconductor Image Sensor) Using Hybrid Bonding to Join the Upper Pixel Chip and Lower Logic Chip
Figure 4: AMD RyzenTM 7 5800X3D CPU Utilizing Hybrid Bonding to Combine L3 Cache with Lower CCD
Figure 5 Evolution of Intel's Foveros Technology
Figure 1 Development of Block Size and I/O Count
Figure 2 Introduction to Hybrid Bonding Process
Figure 3 Sony's CIS (Complementary Metal-Oxide-Semiconductor Image Sensor) Using Hybrid Bonding to Join the Upper Pixel Chip and Lower Logic Chip
Figure 4: AMD RyzenTM 7 5800X3D CPU Utilizing Hybrid Bonding to Combine L3 Cache with Lower CCD
Figure 5 Evolution of Intel's Foveros Technology
